Releases

posted on 06 February 2008 10:00

Rambus has announced that the International Engineering Consortium (IEC) has chosen the Rambus XDR memory architecture as the winner in the 2008 DesignVision Awards category for Semiconductors and ICs (IP).

The IEC DesignVision Awards recognize technologies, applications, products, and services judged to be the most unique and beneficial to the industry.

“This year’s winners exemplify the highest level of innovation in today’s industry,” commented IEC Executive Vice President Roger Plummer. “We are pleased to congratulate Rambus for its XDR memory architecture, which received the 2008 DesignVision Award this week at DesignCon 2008.”

“We take great pride in advancing the state-of-the-art in innovative memory architectures and are honored to be recognized by the IEC,” said Kevin Donnelly, senior vice president of Engineering at Rambus. “The XDR architecture is a total memory system solution that enables blazing fast speeds with the fewest devices, making it ideal for computing and consumer electronics applications.”

Rambus recently announced that Toshiba has taken a license for the XDR memory architecture for its next-generation HDTV chipsets.  In addition, Qimonda has begun shipping its first samples of XDR DRAM, and Elpida has begun shipping 4.8GHz XDR memory, the world’s fastest production DRAM.

Key components enabling the breakthrough performance of the XDR memory architecture are:

- The XDR DRAM, a high-speed memory IC that turbo-charges standard CMOS DRAM cores with a high-speed interface capable of 4.0 GHz data rates providing up to 8 GB/s of bandwidth with a single device.
- The XIO controller IO cell providing the same high-speed signaling capability found on the DRAM, but adding additional enhancements like FlexPhase technology that optimizes timing and eliminates the need for trace length matching.
- The XMC memory controller, a fully synthesizable logical memory controller that is optimized to take advantage of innovations like Dynamic Point-to-Point which provides for capacity expansion while delivering the signal integrity benefits of point-to-point signaling.
- The XCG clock generator providing the system clocks with four programmable outputs, guaranteed to meet the clocking requirements for the XIO and XDR DRAM devices.